The disclosed embodiments of the present invention relate to dividing a frequency of an input clock signal, and more particularly, to a frequency divider capable of generating an output clock signal with a duty cycle different from an input clock signal's duty cycle.
A frequency divider is commonly used for dividing a frequency of an input clock signal to thereby generate an output clock signal with a lower frequency. In a conventional design, the frequency divider aims at changing the frequency without modifying the duty cycle. That is, the duty cycle of the output clock signal generated from the conventional frequency divider is identical to the duty cycle of the input clock signal. However, in certain applications, a clock signal with a duty cycle smaller than an input clock's duty cycle (e.g., 50%) may be desired. For example, regarding a wireless receiver having mixers coupled to the same radio-frequency signal input and a common local oscillator (LO), LO signals each having a duty cycle of 25% are desired by the mixers respectively disposed in the in-phase (I) path and the quadrature (Q) path for reducing the unwanted noise introduced to the following signal processing stage. For example, the common local oscillator generates high-frequency input clock signals with a duty cycle of 50%, and a conventional frequency divider generates low-frequency output clock signals with a duty cycle of 50% according to the high-frequency input clock signals. To obtain desired clock signals with a duty cycle of 25%, a signal processing circuit is particularly implemented to process the output clock signals and/or the input clock signals of the conventional frequency divider. That is, the desired clock signals with the duty cycle of 25% are generated from the signal processing circuit external to the frequency divider.
In a case where each desired clock signal with the duty cycle of 25% is derived from a clock-gating topology which gates one output clock signal of the conventional frequency divider by one input clock signal of the conventional frequency divider, the I/Q imbalance of the receiver is very sensitive to the input clock phase error as the LO signals are generated from the signal processing circuit (i.e., a clock-gating circuit). In another case where each desired clock signal with the duty cycle of 25% is derived from a clock-gating topology which gates one output clock signal of the conventional frequency divider by another output clock signal of the conventional frequency divider, the driving capability of the desired clock signal may be weak due to imperfect rising/falling waveforms of the output clock signals processed by the signal processing circuit (i.e., a clock-gating circuit).
Thus, there is a need for an innovative frequency divider design which can directly generate the output clock signals with the duty cycle different from that of the input clock signal, thereby avoiding the use of the aforementioned clock-gating circuit.